|
Access |
Register |
Address |
Description |
|
(RW) |
32'h00000000 |
Real tcm size is 16KB Internal memory |
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
Memory |
|
Memory |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h00004000 |
Used for 4ND channel Flexa handshaking operation Access address as defined above Internal memory |
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
Memory |
|
Memory |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004080 |
Up-to 16 semaphore cells for Flexa operation |
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
|
[31:16] |
0x0 |
The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004084 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
|
[31:16] |
0x0 |
The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004088 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
|
[31:16] |
0x0 |
The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000408C |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
|
[31:16] |
0x0 |
The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004090 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
|
[31:16] |
0x0 |
The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004094 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
|
[31:16] |
0x0 |
The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004098 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
|
[31:16] |
0x0 |
The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000409C |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
|
[31:16] |
0x0 |
The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000040A0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
|
[31:16] |
0x0 |
The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000040A4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
|
[31:16] |
0x0 |
The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000040A8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
|
[31:16] |
0x0 |
The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000040AC |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
|
[31:16] |
0x0 |
The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000040B0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
|
[31:16] |
0x0 |
The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000040B4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
|
[31:16] |
0x0 |
The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000040B8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
|
[31:16] |
0x0 |
The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000040BC |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
|
[31:16] |
0x0 |
The number of lines in a data segment SemaphoreFlexa cells (xxxx_wrapper_U0.xxxxDhubTop_U0.u_semaHubFlexa.semaFlexaArr0.semaFlexaCellx) is used for dHub channel FLEXA SBI interface handshaking generation; when SEG_LINE field is set to 0, FLEXA SBI interface handshaking is disabled (output is 0, input is ignored) |
|
Access |
Register |
Address |
Description |
|
(WOC-) |
32'h000040C0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
|
|
|
[2:2] |
0x0 |
|
|
|
[3:3] |
0x0 |
|
|
|
[4:4] |
0x0 |
|
|
|
[5:5] |
0x0 |
|
|
|
[6:6] |
0x0 |
|
|
|
[7:7] |
0x0 |
|
|
|
[8:8] |
0x0 |
|
|
|
[9:9] |
0x0 |
|
|
|
[10:10] |
0x0 |
|
|
|
[11:11] |
0x0 |
|
|
|
[12:12] |
0x0 |
|
|
|
[13:13] |
0x0 |
|
|
|
[14:14] |
0x0 |
|
|
|
[15:15] |
0x0 |
All cell 'empty' status |
|
Access |
Register |
Address |
Description |
|
(WOC-) |
32'h000040C4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
|
|
|
[2:2] |
0x0 |
|
|
|
[3:3] |
0x0 |
|
|
|
[4:4] |
0x0 |
|
|
|
[5:5] |
0x0 |
|
|
|
[6:6] |
0x0 |
|
|
|
[7:7] |
0x0 |
|
|
|
[8:8] |
0x0 |
|
|
|
[9:9] |
0x0 |
|
|
|
[10:10] |
0x0 |
|
|
|
[11:11] |
0x0 |
|
|
|
[12:12] |
0x0 |
|
|
|
[13:13] |
0x0 |
|
|
|
[14:14] |
0x0 |
|
|
|
[15:15] |
0x0 |
All cell 'full' status |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h00004100 |
For dHub internal interrupts, also provide semaphore service for external (all channels will be opened to external to access). Channel 0 is used for dHub.HBO interrupt. Channel N+1 is used for dHub.Channel[N] interrupt. Access address as defined above Internal memory |
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
Memory |
|
Memory |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004200 |
Up-to 32 semaphore cells |
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004204 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004208 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000420C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004210 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004214 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004218 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000421C |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004220 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004224 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004228 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000422C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004230 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004234 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004238 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000423C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004240 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004244 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004248 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000424C |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004250 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004254 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004258 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000425C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004260 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004264 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004268 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000426C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004270 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004274 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004278 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000427C |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004280 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004284 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004288 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000428C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004290 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004294 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004298 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000429C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042A0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042A4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042A8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042AC |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042B0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042B4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042B8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042BC |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042C0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042C4 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042C8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042CC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042D0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042D4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042D8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042DC |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042E0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042E4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042E8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042EC |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042F0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042F4 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042F8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000042FC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004300 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004304 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004308 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000430C |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004310 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004314 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004318 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000431C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004320 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004324 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004328 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000432C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004330 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004334 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004338 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000433C |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004340 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004344 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004348 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000434C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004350 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004354 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004358 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000435C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004360 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004364 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004368 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000436C |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004370 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004374 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004378 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000437C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004380 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004384 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004388 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000438C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004390 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004394 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004398 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000439C |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043A0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043A4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043A8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043AC |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043B0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043B4 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043B8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043BC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043C0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043C4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043C8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043CC |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043D0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043D4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043D8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043DC |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043E0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043E4 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043E8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043EC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043F0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043F4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043F8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000043FC |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004400 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004404 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004408 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000440C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004410 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004414 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004418 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000441C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004420 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004424 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004428 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000442C |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004430 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004434 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004438 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000443C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004440 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004444 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004448 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000444C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004450 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004454 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004458 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000445C |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004460 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004464 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004468 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000446C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004470 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004474 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004478 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000447C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004480 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004484 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004488 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000448C |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004490 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004494 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004498 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000449C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044A0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044A4 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044A8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044AC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044B0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044B4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044B8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044BC |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044C0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044C4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044C8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044CC |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044D0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044D4 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044D8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044DC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044E0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044E4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044E8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044EC |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044F0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044F4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044F8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000044FC |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004500 |
|
|
|
Range |
Field |
Reset |
Description |
|
[7:0] |
|
|
|
|
[15:8] |
|
CPU increases PCounter by delta (0 as push 256) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004504 |
|
|
|
Range |
Field |
Reset |
Description |
|
[7:0] |
|
|
|
|
[15:8] |
|
CPU decreases CCounter by delta (0 as pop 256) |
|
Access |
Register |
Address |
Description |
|
(WOC-) |
32'h00004508 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
|
|
|
[2:2] |
0x0 |
|
|
|
[3:3] |
0x0 |
|
|
|
[4:4] |
0x0 |
|
|
|
[5:5] |
0x0 |
|
|
|
[6:6] |
0x0 |
|
|
|
[7:7] |
0x0 |
|
|
|
[8:8] |
0x0 |
|
|
|
[9:9] |
0x0 |
|
|
|
[10:10] |
0x0 |
|
|
|
[11:11] |
0x0 |
|
|
|
[12:12] |
0x0 |
|
|
|
[13:13] |
0x0 |
|
|
|
[14:14] |
0x0 |
|
|
|
[15:15] |
0x0 |
|
|
|
[16:16] |
0x0 |
|
|
|
[17:17] |
0x0 |
|
|
|
[18:18] |
0x0 |
|
|
|
[19:19] |
0x0 |
|
|
|
[20:20] |
0x0 |
|
|
|
[21:21] |
0x0 |
|
|
|
[22:22] |
0x0 |
|
|
|
[23:23] |
0x0 |
|
|
|
[24:24] |
0x0 |
|
|
|
[25:25] |
0x0 |
|
|
|
[26:26] |
0x0 |
|
|
|
[27:27] |
0x0 |
|
|
|
[28:28] |
0x0 |
|
|
|
[29:29] |
0x0 |
|
|
|
[30:30] |
0x0 |
|
|
|
[31:31] |
0x0 |
All cell 'empty' status |
|
Access |
Register |
Address |
Description |
|
(WOC-) |
32'h0000450C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
|
|
|
[2:2] |
0x0 |
|
|
|
[3:3] |
0x0 |
|
|
|
[4:4] |
0x0 |
|
|
|
[5:5] |
0x0 |
|
|
|
[6:6] |
0x0 |
|
|
|
[7:7] |
0x0 |
|
|
|
[8:8] |
0x0 |
|
|
|
[9:9] |
0x0 |
|
|
|
[10:10] |
0x0 |
|
|
|
[11:11] |
0x0 |
|
|
|
[12:12] |
0x0 |
|
|
|
[13:13] |
0x0 |
|
|
|
[14:14] |
0x0 |
|
|
|
[15:15] |
0x0 |
|
|
|
[16:16] |
0x0 |
|
|
|
[17:17] |
0x0 |
|
|
|
[18:18] |
0x0 |
|
|
|
[19:19] |
0x0 |
|
|
|
[20:20] |
0x0 |
|
|
|
[21:21] |
0x0 |
|
|
|
[22:22] |
0x0 |
|
|
|
[23:23] |
0x0 |
|
|
|
[24:24] |
0x0 |
|
|
|
[25:25] |
0x0 |
|
|
|
[26:26] |
0x0 |
|
|
|
[27:27] |
0x0 |
|
|
|
[28:28] |
0x0 |
|
|
|
[29:29] |
0x0 |
|
|
|
[30:30] |
0x0 |
|
|
|
[31:31] |
0x0 |
All cell 'full' status |
|
Access |
Register |
Address |
Description |
|
(WOC-) |
32'h00004510 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
|
|
|
[2:2] |
0x0 |
|
|
|
[3:3] |
0x0 |
|
|
|
[4:4] |
0x0 |
|
|
|
[5:5] |
0x0 |
|
|
|
[6:6] |
0x0 |
|
|
|
[7:7] |
0x0 |
|
|
|
[8:8] |
0x0 |
|
|
|
[9:9] |
0x0 |
|
|
|
[10:10] |
0x0 |
|
|
|
[11:11] |
0x0 |
|
|
|
[12:12] |
0x0 |
|
|
|
[13:13] |
0x0 |
|
|
|
[14:14] |
0x0 |
|
|
|
[15:15] |
0x0 |
|
|
|
[16:16] |
0x0 |
|
|
|
[17:17] |
0x0 |
|
|
|
[18:18] |
0x0 |
|
|
|
[19:19] |
0x0 |
|
|
|
[20:20] |
0x0 |
|
|
|
[21:21] |
0x0 |
|
|
|
[22:22] |
0x0 |
|
|
|
[23:23] |
0x0 |
|
|
|
[24:24] |
0x0 |
|
|
|
[25:25] |
0x0 |
|
|
|
[26:26] |
0x0 |
|
|
|
[27:27] |
0x0 |
|
|
|
[28:28] |
0x0 |
|
|
|
[29:29] |
0x0 |
|
|
|
[30:30] |
0x0 |
|
|
|
[31:31] |
0x0 |
All cell 'almostEmpty' status |
|
Access |
Register |
Address |
Description |
|
(WOC-) |
32'h00004514 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
|
|
|
[2:2] |
0x0 |
|
|
|
[3:3] |
0x0 |
|
|
|
[4:4] |
0x0 |
|
|
|
[5:5] |
0x0 |
|
|
|
[6:6] |
0x0 |
|
|
|
[7:7] |
0x0 |
|
|
|
[8:8] |
0x0 |
|
|
|
[9:9] |
0x0 |
|
|
|
[10:10] |
0x0 |
|
|
|
[11:11] |
0x0 |
|
|
|
[12:12] |
0x0 |
|
|
|
[13:13] |
0x0 |
|
|
|
[14:14] |
0x0 |
|
|
|
[15:15] |
0x0 |
|
|
|
[16:16] |
0x0 |
|
|
|
[17:17] |
0x0 |
|
|
|
[18:18] |
0x0 |
|
|
|
[19:19] |
0x0 |
|
|
|
[20:20] |
0x0 |
|
|
|
[21:21] |
0x0 |
|
|
|
[22:22] |
0x0 |
|
|
|
[23:23] |
0x0 |
|
|
|
[24:24] |
0x0 |
|
|
|
[25:25] |
0x0 |
|
|
|
[26:26] |
0x0 |
|
|
|
[27:27] |
0x0 |
|
|
|
[28:28] |
0x0 |
|
|
|
[29:29] |
0x0 |
|
|
|
[30:30] |
0x0 |
|
|
|
[31:31] |
0x0 |
All cell 'almostFull' status |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h00004600 |
For dHub channels (command/data queues), also provide (unused) FIFO service for external. Channel 2N is used for dHub.Channel[N] command. Channel 2N+1 is used for dHub.Channel[N] data. Access address as defined above Internal memory |
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
Memory |
|
Memory |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004700 |
Up-to 32 semaphore cells |
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004704 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004708 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000470C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004710 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004714 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004718 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000471C |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004720 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004724 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004728 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000472C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004730 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004734 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004738 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000473C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004740 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004744 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004748 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000474C |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004750 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004754 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004758 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000475C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004760 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004764 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004768 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000476C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004770 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004774 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004778 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000477C |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004780 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004784 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004788 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000478C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004790 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004794 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004798 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000479C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047A0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047A4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047A8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047AC |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047B0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047B4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047B8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047BC |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047C0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047C4 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047C8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047CC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047D0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047D4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047D8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047DC |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047E0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047E4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047E8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047EC |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047F0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047F4 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047F8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000047FC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004800 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004804 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004808 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000480C |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004810 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004814 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004818 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000481C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004820 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004824 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004828 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000482C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004830 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004834 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004838 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000483C |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004840 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004844 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004848 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000484C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004850 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004854 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004858 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000485C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004860 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004864 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004868 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000486C |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004870 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004874 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004878 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000487C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004880 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004884 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004888 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000488C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004890 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004894 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004898 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000489C |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048A0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048A4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048A8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048AC |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048B0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048B4 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048B8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048BC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048C0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048C4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048C8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048CC |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048D0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048D4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048D8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048DC |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048E0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048E4 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048E8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048EC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048F0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048F4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048F8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000048FC |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004900 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004904 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004908 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000490C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004910 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004914 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004918 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000491C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004920 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004924 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004928 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000492C |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004930 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004934 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004938 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000493C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004940 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004944 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004948 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000494C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004950 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004954 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004958 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000495C |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004960 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004964 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004968 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000496C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004970 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004974 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004978 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000497C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004980 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004984 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004988 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000498C |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004990 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004994 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004998 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000499C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049A0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049A4 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049A8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049AC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049B0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049B4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049B8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049BC |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049C0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049C4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049C8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049CC |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049D0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049D4 |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049D8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049DC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049E0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049E4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049E8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0xF |
Max level of semaphore Note: write this register will trigger counter reset |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049EC |
Interrupt mask for 3 CPUs |
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049F0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049F4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Enable interrupt on 'empty' condition |
|
|
[1:1] |
0x0 |
Enable interrupt on 'full' condition |
|
|
[2:2] |
0x0 |
Enable interrupt on 'almostEmpty' condition |
|
|
[3:3] |
0x0 |
Enable interrupt on 'almostFull' condition |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049F8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000049FC |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
|
|
|
[3:2] |
0x0 |
Selects almost full and almost empty threshold levels 2'b0: 1/2 2'b1: 1/4 2'b2: 3/4 2'b3: 1/8 for aEmp 7/8 for aFull For aFull, the aFull flag is set when >= level chosen For aEmp, the aEmp flag is set when <= level chosen. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004A00 |
|
|
|
Range |
Field |
Reset |
Description |
|
[7:0] |
|
|
|
|
[15:8] |
|
CPU increases PCounter by delta (0 as push 256) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004A04 |
|
|
|
Range |
Field |
Reset |
Description |
|
[7:0] |
|
|
|
|
[15:8] |
|
CPU decreases CCounter by delta (0 as pop 256) |
|
Access |
Register |
Address |
Description |
|
(WOC-) |
32'h00004A08 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
|
|
|
[2:2] |
0x0 |
|
|
|
[3:3] |
0x0 |
|
|
|
[4:4] |
0x0 |
|
|
|
[5:5] |
0x0 |
|
|
|
[6:6] |
0x0 |
|
|
|
[7:7] |
0x0 |
|
|
|
[8:8] |
0x0 |
|
|
|
[9:9] |
0x0 |
|
|
|
[10:10] |
0x0 |
|
|
|
[11:11] |
0x0 |
|
|
|
[12:12] |
0x0 |
|
|
|
[13:13] |
0x0 |
|
|
|
[14:14] |
0x0 |
|
|
|
[15:15] |
0x0 |
|
|
|
[16:16] |
0x0 |
|
|
|
[17:17] |
0x0 |
|
|
|
[18:18] |
0x0 |
|
|
|
[19:19] |
0x0 |
|
|
|
[20:20] |
0x0 |
|
|
|
[21:21] |
0x0 |
|
|
|
[22:22] |
0x0 |
|
|
|
[23:23] |
0x0 |
|
|
|
[24:24] |
0x0 |
|
|
|
[25:25] |
0x0 |
|
|
|
[26:26] |
0x0 |
|
|
|
[27:27] |
0x0 |
|
|
|
[28:28] |
0x0 |
|
|
|
[29:29] |
0x0 |
|
|
|
[30:30] |
0x0 |
|
|
|
[31:31] |
0x0 |
All cell 'empty' status |
|
Access |
Register |
Address |
Description |
|
(WOC-) |
32'h00004A0C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
|
|
|
[2:2] |
0x0 |
|
|
|
[3:3] |
0x0 |
|
|
|
[4:4] |
0x0 |
|
|
|
[5:5] |
0x0 |
|
|
|
[6:6] |
0x0 |
|
|
|
[7:7] |
0x0 |
|
|
|
[8:8] |
0x0 |
|
|
|
[9:9] |
0x0 |
|
|
|
[10:10] |
0x0 |
|
|
|
[11:11] |
0x0 |
|
|
|
[12:12] |
0x0 |
|
|
|
[13:13] |
0x0 |
|
|
|
[14:14] |
0x0 |
|
|
|
[15:15] |
0x0 |
|
|
|
[16:16] |
0x0 |
|
|
|
[17:17] |
0x0 |
|
|
|
[18:18] |
0x0 |
|
|
|
[19:19] |
0x0 |
|
|
|
[20:20] |
0x0 |
|
|
|
[21:21] |
0x0 |
|
|
|
[22:22] |
0x0 |
|
|
|
[23:23] |
0x0 |
|
|
|
[24:24] |
0x0 |
|
|
|
[25:25] |
0x0 |
|
|
|
[26:26] |
0x0 |
|
|
|
[27:27] |
0x0 |
|
|
|
[28:28] |
0x0 |
|
|
|
[29:29] |
0x0 |
|
|
|
[30:30] |
0x0 |
|
|
|
[31:31] |
0x0 |
All cell 'full' status |
|
Access |
Register |
Address |
Description |
|
(WOC-) |
32'h00004A10 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
|
|
|
[2:2] |
0x0 |
|
|
|
[3:3] |
0x0 |
|
|
|
[4:4] |
0x0 |
|
|
|
[5:5] |
0x0 |
|
|
|
[6:6] |
0x0 |
|
|
|
[7:7] |
0x0 |
|
|
|
[8:8] |
0x0 |
|
|
|
[9:9] |
0x0 |
|
|
|
[10:10] |
0x0 |
|
|
|
[11:11] |
0x0 |
|
|
|
[12:12] |
0x0 |
|
|
|
[13:13] |
0x0 |
|
|
|
[14:14] |
0x0 |
|
|
|
[15:15] |
0x0 |
|
|
|
[16:16] |
0x0 |
|
|
|
[17:17] |
0x0 |
|
|
|
[18:18] |
0x0 |
|
|
|
[19:19] |
0x0 |
|
|
|
[20:20] |
0x0 |
|
|
|
[21:21] |
0x0 |
|
|
|
[22:22] |
0x0 |
|
|
|
[23:23] |
0x0 |
|
|
|
[24:24] |
0x0 |
|
|
|
[25:25] |
0x0 |
|
|
|
[26:26] |
0x0 |
|
|
|
[27:27] |
0x0 |
|
|
|
[28:28] |
0x0 |
|
|
|
[29:29] |
0x0 |
|
|
|
[30:30] |
0x0 |
|
|
|
[31:31] |
0x0 |
All cell 'almostEmpty' status |
|
Access |
Register |
Address |
Description |
|
(WOC-) |
32'h00004A14 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
|
|
|
[1:1] |
0x0 |
|
|
|
[2:2] |
0x0 |
|
|
|
[3:3] |
0x0 |
|
|
|
[4:4] |
0x0 |
|
|
|
[5:5] |
0x0 |
|
|
|
[6:6] |
0x0 |
|
|
|
[7:7] |
0x0 |
|
|
|
[8:8] |
0x0 |
|
|
|
[9:9] |
0x0 |
|
|
|
[10:10] |
0x0 |
|
|
|
[11:11] |
0x0 |
|
|
|
[12:12] |
0x0 |
|
|
|
[13:13] |
0x0 |
|
|
|
[14:14] |
0x0 |
|
|
|
[15:15] |
0x0 |
|
|
|
[16:16] |
0x0 |
|
|
|
[17:17] |
0x0 |
|
|
|
[18:18] |
0x0 |
|
|
|
[19:19] |
0x0 |
|
|
|
[20:20] |
0x0 |
|
|
|
[21:21] |
0x0 |
|
|
|
[22:22] |
0x0 |
|
|
|
[23:23] |
0x0 |
|
|
|
[24:24] |
0x0 |
|
|
|
[25:25] |
0x0 |
|
|
|
[26:26] |
0x0 |
|
|
|
[27:27] |
0x0 |
|
|
|
[28:28] |
0x0 |
|
|
|
[29:29] |
0x0 |
|
|
|
[30:30] |
0x0 |
|
|
|
[31:31] |
0x0 |
All cell 'almostFull' status |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B00 |
Up-to 32 FIFO channels FiFo[N] is controlled by HBO.FiFoCtl.Channel[N] |
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B04 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B08 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B0C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B10 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B14 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B18 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B1C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B20 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B24 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B28 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B2C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B30 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B34 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B38 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B3C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B40 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B44 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B48 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B4C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B50 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B54 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B58 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B5C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B60 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B64 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B68 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B6C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B70 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B74 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B78 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B7C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B80 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B84 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B88 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B8C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B90 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B94 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B98 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004B9C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BA0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BA4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BA8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BAC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BB0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BB4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BB8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BBC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BC0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BC4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BC8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BCC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BD0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BD4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BD8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BDC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BE0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BE4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BE8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BEC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BF0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BF4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BF8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004BFC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C00 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C04 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C08 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C0C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C10 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C14 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C18 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C1C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C20 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C24 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C28 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C2C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C30 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C34 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C38 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C3C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C40 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C44 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C48 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C4C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C50 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C54 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C58 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C5C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C60 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C64 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C68 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C6C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C70 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C74 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C78 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C7C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C80 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C84 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C88 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C8C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C90 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C94 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C98 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004C9C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CA0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CA4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CA8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CAC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CB0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CB4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CB8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CBC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CC0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CC4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CC8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CCC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CD0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CD4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CD8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CDC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CE0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CE4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CE8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CEC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CF0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[19:0] |
|
Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. Note: aligned with base SRAM data bus. For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CF4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CF8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to clear FIFO pointers to 0. Note : CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. Do not restart the channel when clear operation is in process. HW will make sure there is no pending transactions before execute the clear operation. Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004CFC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
No support for now |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h00004D00 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
|
Per channel status Indicate the clear operation status. 1: clear is in process. 0 : clear is done. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E00 |
Up-to 16 channels |
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
|
Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB. |
|
|
[4:4] |
0x0 |
Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO |
|
|
[5:5] |
0x0 |
Write 1 to enable cmd looping support; 0 to turn off |
|
|
[6:6] |
0x0 |
0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty). |
|
|
[7:7] |
0x0 |
This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly. |
|
|
[8:8] |
0x0 |
This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E04 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E08 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
AWQOS value when low priority |
|
|
[7:4] |
0xF |
AWQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E0C |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
ARQOS value when low priority |
|
|
[7:4] |
0xF |
ARQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E10 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable AWLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable AWPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd |
|
|
[13:11] |
0x0 |
Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware |
|
|
[14:14] |
0x0 |
0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E14 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable ARLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable ARPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd |
|
|
[14:11] |
0x0 |
Programmable AWCACHE[3:0] value |
|
|
[15:15] |
0x0 |
0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E18 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E1C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the channel controller state |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E20 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E24 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
|
Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB. |
|
|
[4:4] |
0x0 |
Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO |
|
|
[5:5] |
0x0 |
Write 1 to enable cmd looping support; 0 to turn off |
|
|
[6:6] |
0x0 |
0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty). |
|
|
[7:7] |
0x0 |
This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly. |
|
|
[8:8] |
0x0 |
This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E28 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E2C |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
AWQOS value when low priority |
|
|
[7:4] |
0xF |
AWQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E30 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
ARQOS value when low priority |
|
|
[7:4] |
0xF |
ARQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E34 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable AWLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable AWPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd |
|
|
[13:11] |
0x0 |
Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware |
|
|
[14:14] |
0x0 |
0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E38 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable ARLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable ARPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd |
|
|
[14:11] |
0x0 |
Programmable AWCACHE[3:0] value |
|
|
[15:15] |
0x0 |
0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E3C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E40 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the channel controller state |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E44 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E48 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
|
Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB. |
|
|
[4:4] |
0x0 |
Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO |
|
|
[5:5] |
0x0 |
Write 1 to enable cmd looping support; 0 to turn off |
|
|
[6:6] |
0x0 |
0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty). |
|
|
[7:7] |
0x0 |
This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly. |
|
|
[8:8] |
0x0 |
This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E4C |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E50 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
AWQOS value when low priority |
|
|
[7:4] |
0xF |
AWQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E54 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
ARQOS value when low priority |
|
|
[7:4] |
0xF |
ARQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E58 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable AWLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable AWPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd |
|
|
[13:11] |
0x0 |
Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware |
|
|
[14:14] |
0x0 |
0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E5C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable ARLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable ARPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd |
|
|
[14:11] |
0x0 |
Programmable AWCACHE[3:0] value |
|
|
[15:15] |
0x0 |
0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E60 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E64 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the channel controller state |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E68 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E6C |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
|
Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB. |
|
|
[4:4] |
0x0 |
Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO |
|
|
[5:5] |
0x0 |
Write 1 to enable cmd looping support; 0 to turn off |
|
|
[6:6] |
0x0 |
0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty). |
|
|
[7:7] |
0x0 |
This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly. |
|
|
[8:8] |
0x0 |
This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E70 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E74 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
AWQOS value when low priority |
|
|
[7:4] |
0xF |
AWQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E78 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
ARQOS value when low priority |
|
|
[7:4] |
0xF |
ARQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E7C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable AWLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable AWPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd |
|
|
[13:11] |
0x0 |
Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware |
|
|
[14:14] |
0x0 |
0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E80 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable ARLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable ARPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd |
|
|
[14:11] |
0x0 |
Programmable AWCACHE[3:0] value |
|
|
[15:15] |
0x0 |
0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E84 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E88 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the channel controller state |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E8C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E90 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
|
Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB. |
|
|
[4:4] |
0x0 |
Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO |
|
|
[5:5] |
0x0 |
Write 1 to enable cmd looping support; 0 to turn off |
|
|
[6:6] |
0x0 |
0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty). |
|
|
[7:7] |
0x0 |
This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly. |
|
|
[8:8] |
0x0 |
This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E94 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E98 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
AWQOS value when low priority |
|
|
[7:4] |
0xF |
AWQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004E9C |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
ARQOS value when low priority |
|
|
[7:4] |
0xF |
ARQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004EA0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable AWLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable AWPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd |
|
|
[13:11] |
0x0 |
Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware |
|
|
[14:14] |
0x0 |
0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004EA4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable ARLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable ARPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd |
|
|
[14:11] |
0x0 |
Programmable AWCACHE[3:0] value |
|
|
[15:15] |
0x0 |
0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004EA8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004EAC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the channel controller state |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004EB0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004EB4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
|
Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB. |
|
|
[4:4] |
0x0 |
Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO |
|
|
[5:5] |
0x0 |
Write 1 to enable cmd looping support; 0 to turn off |
|
|
[6:6] |
0x0 |
0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty). |
|
|
[7:7] |
0x0 |
This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly. |
|
|
[8:8] |
0x0 |
This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004EB8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004EBC |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
AWQOS value when low priority |
|
|
[7:4] |
0xF |
AWQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004EC0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
ARQOS value when low priority |
|
|
[7:4] |
0xF |
ARQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004EC4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable AWLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable AWPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd |
|
|
[13:11] |
0x0 |
Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware |
|
|
[14:14] |
0x0 |
0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004EC8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable ARLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable ARPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd |
|
|
[14:11] |
0x0 |
Programmable AWCACHE[3:0] value |
|
|
[15:15] |
0x0 |
0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004ECC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004ED0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the channel controller state |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004ED4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004ED8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
|
Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB. |
|
|
[4:4] |
0x0 |
Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO |
|
|
[5:5] |
0x0 |
Write 1 to enable cmd looping support; 0 to turn off |
|
|
[6:6] |
0x0 |
0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty). |
|
|
[7:7] |
0x0 |
This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly. |
|
|
[8:8] |
0x0 |
This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004EDC |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004EE0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
AWQOS value when low priority |
|
|
[7:4] |
0xF |
AWQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004EE4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
ARQOS value when low priority |
|
|
[7:4] |
0xF |
ARQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004EE8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable AWLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable AWPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd |
|
|
[13:11] |
0x0 |
Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware |
|
|
[14:14] |
0x0 |
0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004EEC |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable ARLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable ARPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd |
|
|
[14:11] |
0x0 |
Programmable AWCACHE[3:0] value |
|
|
[15:15] |
0x0 |
0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004EF0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004EF4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the channel controller state |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004EF8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004EFC |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
|
Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB. |
|
|
[4:4] |
0x0 |
Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO |
|
|
[5:5] |
0x0 |
Write 1 to enable cmd looping support; 0 to turn off |
|
|
[6:6] |
0x0 |
0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty). |
|
|
[7:7] |
0x0 |
This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly. |
|
|
[8:8] |
0x0 |
This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F00 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F04 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
AWQOS value when low priority |
|
|
[7:4] |
0xF |
AWQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F08 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
ARQOS value when low priority |
|
|
[7:4] |
0xF |
ARQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F0C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable AWLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable AWPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd |
|
|
[13:11] |
0x0 |
Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware |
|
|
[14:14] |
0x0 |
0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F10 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable ARLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable ARPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd |
|
|
[14:11] |
0x0 |
Programmable AWCACHE[3:0] value |
|
|
[15:15] |
0x0 |
0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F14 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F18 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the channel controller state |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F1C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F20 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
|
Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB. |
|
|
[4:4] |
0x0 |
Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO |
|
|
[5:5] |
0x0 |
Write 1 to enable cmd looping support; 0 to turn off |
|
|
[6:6] |
0x0 |
0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty). |
|
|
[7:7] |
0x0 |
This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly. |
|
|
[8:8] |
0x0 |
This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F24 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F28 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
AWQOS value when low priority |
|
|
[7:4] |
0xF |
AWQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F2C |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
ARQOS value when low priority |
|
|
[7:4] |
0xF |
ARQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F30 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable AWLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable AWPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd |
|
|
[13:11] |
0x0 |
Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware |
|
|
[14:14] |
0x0 |
0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F34 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable ARLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable ARPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd |
|
|
[14:11] |
0x0 |
Programmable AWCACHE[3:0] value |
|
|
[15:15] |
0x0 |
0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F38 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F3C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the channel controller state |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F40 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F44 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
|
Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB. |
|
|
[4:4] |
0x0 |
Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO |
|
|
[5:5] |
0x0 |
Write 1 to enable cmd looping support; 0 to turn off |
|
|
[6:6] |
0x0 |
0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty). |
|
|
[7:7] |
0x0 |
This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly. |
|
|
[8:8] |
0x0 |
This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F48 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F4C |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
AWQOS value when low priority |
|
|
[7:4] |
0xF |
AWQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F50 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
ARQOS value when low priority |
|
|
[7:4] |
0xF |
ARQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F54 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable AWLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable AWPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd |
|
|
[13:11] |
0x0 |
Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware |
|
|
[14:14] |
0x0 |
0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F58 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable ARLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable ARPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd |
|
|
[14:11] |
0x0 |
Programmable AWCACHE[3:0] value |
|
|
[15:15] |
0x0 |
0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F5C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F60 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the channel controller state |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F64 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F68 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
|
Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB. |
|
|
[4:4] |
0x0 |
Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO |
|
|
[5:5] |
0x0 |
Write 1 to enable cmd looping support; 0 to turn off |
|
|
[6:6] |
0x0 |
0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty). |
|
|
[7:7] |
0x0 |
This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly. |
|
|
[8:8] |
0x0 |
This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F6C |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F70 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
AWQOS value when low priority |
|
|
[7:4] |
0xF |
AWQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F74 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
ARQOS value when low priority |
|
|
[7:4] |
0xF |
ARQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F78 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable AWLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable AWPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd |
|
|
[13:11] |
0x0 |
Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware |
|
|
[14:14] |
0x0 |
0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F7C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable ARLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable ARPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd |
|
|
[14:11] |
0x0 |
Programmable AWCACHE[3:0] value |
|
|
[15:15] |
0x0 |
0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F80 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F84 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the channel controller state |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F88 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F8C |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
|
Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB. |
|
|
[4:4] |
0x0 |
Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO |
|
|
[5:5] |
0x0 |
Write 1 to enable cmd looping support; 0 to turn off |
|
|
[6:6] |
0x0 |
0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty). |
|
|
[7:7] |
0x0 |
This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly. |
|
|
[8:8] |
0x0 |
This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F90 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F94 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
AWQOS value when low priority |
|
|
[7:4] |
0xF |
AWQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F98 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
ARQOS value when low priority |
|
|
[7:4] |
0xF |
ARQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004F9C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable AWLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable AWPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd |
|
|
[13:11] |
0x0 |
Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware |
|
|
[14:14] |
0x0 |
0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FA0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable ARLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable ARPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd |
|
|
[14:11] |
0x0 |
Programmable AWCACHE[3:0] value |
|
|
[15:15] |
0x0 |
0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FA4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FA8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the channel controller state |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FAC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FB0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
|
Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB. |
|
|
[4:4] |
0x0 |
Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO |
|
|
[5:5] |
0x0 |
Write 1 to enable cmd looping support; 0 to turn off |
|
|
[6:6] |
0x0 |
0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty). |
|
|
[7:7] |
0x0 |
This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly. |
|
|
[8:8] |
0x0 |
This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FB4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FB8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
AWQOS value when low priority |
|
|
[7:4] |
0xF |
AWQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FBC |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
ARQOS value when low priority |
|
|
[7:4] |
0xF |
ARQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FC0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable AWLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable AWPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd |
|
|
[13:11] |
0x0 |
Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware |
|
|
[14:14] |
0x0 |
0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FC4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable ARLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable ARPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd |
|
|
[14:11] |
0x0 |
Programmable AWCACHE[3:0] value |
|
|
[15:15] |
0x0 |
0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FC8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FCC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the channel controller state |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FD0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FD4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
|
Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB. |
|
|
[4:4] |
0x0 |
Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO |
|
|
[5:5] |
0x0 |
Write 1 to enable cmd looping support; 0 to turn off |
|
|
[6:6] |
0x0 |
0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty). |
|
|
[7:7] |
0x0 |
This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly. |
|
|
[8:8] |
0x0 |
This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FD8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FDC |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
AWQOS value when low priority |
|
|
[7:4] |
0xF |
AWQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FE0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
ARQOS value when low priority |
|
|
[7:4] |
0xF |
ARQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FE4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable AWLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable AWPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd |
|
|
[13:11] |
0x0 |
Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware |
|
|
[14:14] |
0x0 |
0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FE8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable ARLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable ARPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd |
|
|
[14:11] |
0x0 |
Programmable AWCACHE[3:0] value |
|
|
[15:15] |
0x0 |
0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FEC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FF0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the channel controller state |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FF4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FF8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
|
Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB. |
|
|
[4:4] |
0x0 |
Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO |
|
|
[5:5] |
0x0 |
Write 1 to enable cmd looping support; 0 to turn off |
|
|
[6:6] |
0x0 |
0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty). |
|
|
[7:7] |
0x0 |
This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly. |
|
|
[8:8] |
0x0 |
This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00004FFC |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005000 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
AWQOS value when low priority |
|
|
[7:4] |
0xF |
AWQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005004 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
ARQOS value when low priority |
|
|
[7:4] |
0xF |
ARQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005008 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable AWLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable AWPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd |
|
|
[13:11] |
0x0 |
Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware |
|
|
[14:14] |
0x0 |
0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000500C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable ARLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable ARPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd |
|
|
[14:11] |
0x0 |
Programmable AWCACHE[3:0] value |
|
|
[15:15] |
0x0 |
0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005010 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005014 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the channel controller state |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005018 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000501C |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
|
Minimum transfer unit of the channel Values > 9 are set to 4096byte Important note for 64-bit dHubs: Cannot set to values >= 9. A full 256-beat burst of 8-bytes is 2048 bytes. Behavior is unpredictable if set to MTU = 4KB. |
|
|
[4:4] |
0x0 |
Write 1 to turn on QoS detection When QoS detection is on, AxQOS values is dynamically chosen from AxQOS.HI and AxQOS.LO |
|
|
[5:5] |
0x0 |
Write 1 to enable cmd looping support; 0 to turn off |
|
|
[6:6] |
0x0 |
0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty). |
|
|
[7:7] |
0x0 |
This parameter will only apply to read channels. It will affect 1D dHub command for the channel. When scan is set to 1 (invScan), the data (beat) inside the dHub command will be fetched in the inverse order. ie. The data from the last address will come first and the data (beat) from the first address will come lastly. |
|
|
[8:8] |
0x0 |
This parameter will only apply to read channels. It will affect 2D channels. When scan is set to 1 (invScan), The last address line (1D command) will be fetched first, and the first address line will be fetched lastly. Note: This parameter cannot be set to 1 if MTU results in > 256byte. The cost of using a > 256byte buffer in current architecture is too much. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005020 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
Maps a read channel to this ROB index. A user can configure from 1 to the number of read channel number of hardware ROBs. (Using .cfg) This field will map this channel if it is a read channel to the ROB specified here. Has no effect on write channels. ROBs are indexed from 0 to NUM_ROB-1 If the setting is invalid, ie ID > NUM_ROB-1, then HW will remap it to 0. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005024 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
AWQOS value when low priority |
|
|
[7:4] |
0xF |
AWQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005028 |
|
|
|
Range |
Field |
Reset |
Description |
|
[3:0] |
0x0 |
ARQOS value when low priority |
|
|
[7:4] |
0xF |
ARQOS value when high priority |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000502C |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable AWLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable AWPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable AWUSER[15:10] value. Whether upper four bits is sent out the AXI interface is determined by USER_HI_EN bit. AWUSER[9:0] is controlled by dHubCmd |
|
|
[13:11] |
0x0 |
Programmable AWCACHE[3:1] value. AWCACHE[0], non-bufferable bit, is controlled by dHub hardware |
|
|
[14:14] |
0x0 |
0: AWUSER[15:12] = Channel ID 1: AWUSER[15:12] = AWPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of AWUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005030 |
|
|
|
Range |
Field |
Reset |
Description |
|
[1:0] |
0x0 |
Programmable ARLOCK[1:0] value |
|
|
[4:2] |
0x0 |
Programmable ARPROT[2:0] value |
|
|
[10:5] |
0x0 |
Programmable ARUSER[15:10] value. ARUSER[9:0] is controlled by dHubCmd |
|
|
[14:11] |
0x0 |
Programmable AWCACHE[3:0] value |
|
|
[15:15] |
0x0 |
0: ARUSER[15:12] = Channel ID 1: ARUSER[15:12] = ARPARAMS.USER[5:2] If user does not configure dHub with Multi ID Enabled but wants to identify the originating channel of the transaction, the user can use the MSB of ARUSER for this purpose. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005034 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005038 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the channel controller state |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000503C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to start the data flushing process. Invalid for read (M2H) channels end dHubChannel |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h00005040 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
Per channel status 0: no ongoing command is being processed, and no flushing is taking place 1: channel controller is busy |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h00005044 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
Per channel status 0: Response queue is empty, meaning no outstanding AXI transactions 1: there exist some outstanding AXI transactions |
|
Access |
Register |
Address |
Description |
|
(RW-) |
32'h00005048 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write one to this register will trigger gate-keeper to take over the AXI bus. |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h0000504C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x1 |
After gate-keeper take over the AXI bus, it will assert this bit once there is no outstanding transactions on AXI bus. |
|
Access |
Register |
Address |
Description |
|
(P) |
32'h00005050 |
|
|
|
Range |
Field |
Reset |
Description |
|
[7:0] |
0x0 |
|
|
|
[15:8] |
0x0 |
Flow control parameter for read and write axi master. clkCnt=(alpha*bstLen) > >4. This # of clock cycles will be blocked for the axi master after an axi command with the burst length of “bstLen”. When set alpha to be 0, the master will never be blocked. |
|
Access |
Register |
Address |
Description |
|
(P) |
32'h00005054 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x0 |
|
|
|
[31:16] |
0x0 |
Axi command collection. The counter value indicate read/write do the command collection for # of clock cycles, start from the first command pushed to an empty command Q. Here are the conditions that will trigger the Axi master to send out command. Cmd Q full or the counter count down to “0” from the programmed value. Set the counter to 0 will disable the command collection. |
|
Access |
Register |
Address |
Description |
|
(P) |
32'h00005058 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
When 0, the read channel will have AXI_ID = ROB_ID. ROB_ID is dependent on which ROB the read channel is mapped to in dHubChannel.ROB_MAP.ID write channel will have AXI_ID = 0. Write one to this register to enable multi-ID support. Multi-ID when enabled will issue AXI IDs = channel number for each AXI transaction. Note: If set to 1, the read slave return must never interleave RIDs. If slave return interleaves RID, this bit must never be set to 1. end dHubReg |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005100 |
Up-to 16 2D channels. 2D Channel[N] is connected to dHub.Channel[N] command queue, that is, dHub.HBO.Channel[2N] Note: Number of 2D channels could be less than dHub channels (rest of are 1D only) |
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
|
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005104 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
Line stride size in bytes |
|
|
[28:16] |
|
Number of lines in buffer. Size of 0 is forbidden. |
|
|
[30:29] |
|
Size of line-loop for choosing dHubCmdHDR 0 is treated as 4 |
|
|
[31:31] |
|
1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005108 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000510C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the 2D engine. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005110 |
Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D |
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005114 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005118 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000511C |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005120 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
|
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005124 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
Line stride size in bytes |
|
|
[28:16] |
|
Number of lines in buffer. Size of 0 is forbidden. |
|
|
[30:29] |
|
Size of line-loop for choosing dHubCmdHDR 0 is treated as 4 |
|
|
[31:31] |
|
1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005128 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000512C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the 2D engine. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005130 |
Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D |
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005134 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005138 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000513C |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005140 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
|
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005144 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
Line stride size in bytes |
|
|
[28:16] |
|
Number of lines in buffer. Size of 0 is forbidden. |
|
|
[30:29] |
|
Size of line-loop for choosing dHubCmdHDR 0 is treated as 4 |
|
|
[31:31] |
|
1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005148 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000514C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the 2D engine. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005150 |
Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D |
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005154 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005158 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000515C |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005160 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
|
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005164 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
Line stride size in bytes |
|
|
[28:16] |
|
Number of lines in buffer. Size of 0 is forbidden. |
|
|
[30:29] |
|
Size of line-loop for choosing dHubCmdHDR 0 is treated as 4 |
|
|
[31:31] |
|
1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005168 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000516C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the 2D engine. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005170 |
Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D |
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005174 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005178 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000517C |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005180 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
|
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005184 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
Line stride size in bytes |
|
|
[28:16] |
|
Number of lines in buffer. Size of 0 is forbidden. |
|
|
[30:29] |
|
Size of line-loop for choosing dHubCmdHDR 0 is treated as 4 |
|
|
[31:31] |
|
1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005188 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000518C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the 2D engine. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005190 |
Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D |
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005194 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005198 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000519C |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051A0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
|
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051A4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
Line stride size in bytes |
|
|
[28:16] |
|
Number of lines in buffer. Size of 0 is forbidden. |
|
|
[30:29] |
|
Size of line-loop for choosing dHubCmdHDR 0 is treated as 4 |
|
|
[31:31] |
|
1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051A8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051AC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the 2D engine. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051B0 |
Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D |
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051B4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051B8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051BC |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051C0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
|
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051C4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
Line stride size in bytes |
|
|
[28:16] |
|
Number of lines in buffer. Size of 0 is forbidden. |
|
|
[30:29] |
|
Size of line-loop for choosing dHubCmdHDR 0 is treated as 4 |
|
|
[31:31] |
|
1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051C8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051CC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the 2D engine. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051D0 |
Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D |
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051D4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051D8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051DC |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051E0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
|
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051E4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
Line stride size in bytes |
|
|
[28:16] |
|
Number of lines in buffer. Size of 0 is forbidden. |
|
|
[30:29] |
|
Size of line-loop for choosing dHubCmdHDR 0 is treated as 4 |
|
|
[31:31] |
|
1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051E8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051EC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the 2D engine. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051F0 |
Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D |
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051F4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051F8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000051FC |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005200 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
|
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005204 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
Line stride size in bytes |
|
|
[28:16] |
|
Number of lines in buffer. Size of 0 is forbidden. |
|
|
[30:29] |
|
Size of line-loop for choosing dHubCmdHDR 0 is treated as 4 |
|
|
[31:31] |
|
1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005208 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000520C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the 2D engine. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005210 |
Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D |
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005214 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005218 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000521C |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005220 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
|
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005224 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
Line stride size in bytes |
|
|
[28:16] |
|
Number of lines in buffer. Size of 0 is forbidden. |
|
|
[30:29] |
|
Size of line-loop for choosing dHubCmdHDR 0 is treated as 4 |
|
|
[31:31] |
|
1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005228 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000522C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the 2D engine. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005230 |
Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D |
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005234 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005238 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000523C |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005240 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
|
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005244 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
Line stride size in bytes |
|
|
[28:16] |
|
Number of lines in buffer. Size of 0 is forbidden. |
|
|
[30:29] |
|
Size of line-loop for choosing dHubCmdHDR 0 is treated as 4 |
|
|
[31:31] |
|
1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005248 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000524C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the 2D engine. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005250 |
Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D |
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005254 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005258 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000525C |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005260 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
|
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005264 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
Line stride size in bytes |
|
|
[28:16] |
|
Number of lines in buffer. Size of 0 is forbidden. |
|
|
[30:29] |
|
Size of line-loop for choosing dHubCmdHDR 0 is treated as 4 |
|
|
[31:31] |
|
1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005268 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000526C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the 2D engine. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005270 |
Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D |
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005274 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005278 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000527C |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005280 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
|
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005284 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
Line stride size in bytes |
|
|
[28:16] |
|
Number of lines in buffer. Size of 0 is forbidden. |
|
|
[30:29] |
|
Size of line-loop for choosing dHubCmdHDR 0 is treated as 4 |
|
|
[31:31] |
|
1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005288 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000528C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the 2D engine. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005290 |
Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D |
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005294 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005298 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000529C |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052A0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
|
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052A4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
Line stride size in bytes |
|
|
[28:16] |
|
Number of lines in buffer. Size of 0 is forbidden. |
|
|
[30:29] |
|
Size of line-loop for choosing dHubCmdHDR 0 is treated as 4 |
|
|
[31:31] |
|
1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052A8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052AC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the 2D engine. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052B0 |
Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D |
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052B4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052B8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052BC |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052C0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
|
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052C4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
Line stride size in bytes |
|
|
[28:16] |
|
Number of lines in buffer. Size of 0 is forbidden. |
|
|
[30:29] |
|
Size of line-loop for choosing dHubCmdHDR 0 is treated as 4 |
|
|
[31:31] |
|
1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052C8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052CC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the 2D engine. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052D0 |
Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D |
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052D4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052D8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052DC |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052E0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
|
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052E4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
Line stride size in bytes |
|
|
[28:16] |
|
Number of lines in buffer. Size of 0 is forbidden. |
|
|
[30:29] |
|
Size of line-loop for choosing dHubCmdHDR 0 is treated as 4 |
|
|
[31:31] |
|
1: raise interrupt upon whole 2D command finish. 1: set the last 1D command interrupt bit. 0 : use the default 1D command interrupt bit. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052E8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel; 0 to pause the channel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052EC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
|
Write anything to reset the 2D engine. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052F0 |
Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop end dHubCmd2D |
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052F4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052F8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000052FC |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
amount of data to be transferred, in bytes or MTU. Size of 0 is forbidden. |
|
|
[16:16] |
|
0: size given in bytes; 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
|
|
[17:17] |
|
0: semaphore operations applied on dHubCmd level 1: semaphore operations applied on MTU level |
|
|
[22:18] |
|
ID of semaphore to check before cmd / MTU; 0 indicates semaphore check is disabled |
|
|
[27:23] |
|
ID of semaphore to update after cmd / MTU; 0 indicates semaphore update is disabled |
|
|
[28:28] |
|
1: raise interrupt upon command finish |
|
|
[29:29] |
|
0: AxQOS selection between HI value and LO value is a function of FIFO occupancy 1: AxQOS selection between HI value and LO value is determined by qosSel in dHubCmd |
|
|
[30:30] |
|
Changes the way the *SemId 10-bit field are used. 0: updSemId and chkSemId operates as normal, AxUser[9:0] = 0; 1: Disables updSemId and chkSemId, AxUser[9:0] = {updSemId[4:0], chkSemId[4:0]} |
|
|
[31:31] |
|
0 : Select dHubChannel.AxQOS.LO value 1 : Select dHubChannel.AxQOS.HI value end dHubCmdHDR |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005300 |
Up-to 16 2ND channels. 2ND Channel[N] is connected to dHub.Channel[N] command queue, that is, dHub.HBO.Channel[2N] Note: 2ND engines are instantiated in the same way as the old 2D engine. It is allowed to have multiple 1D, 2D, 2ND and 4ND channels in a dHub. Restriction is each channel can only have one type. |
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005304 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005308 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000530C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005310 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005314 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005318 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 2D buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000531C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 2D engine. end dHubCmd2ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005320 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005324 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005328 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000532C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005330 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005334 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005338 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 2D buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000533C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 2D engine. end dHubCmd2ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005340 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005344 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005348 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000534C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005350 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005354 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005358 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 2D buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000535C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 2D engine. end dHubCmd2ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005360 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005364 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005368 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000536C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005370 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005374 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005378 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 2D buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000537C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 2D engine. end dHubCmd2ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005380 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005384 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005388 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000538C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005390 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005394 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005398 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 2D buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000539C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 2D engine. end dHubCmd2ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053A0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053A4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053A8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053AC |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053B0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053B4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053B8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 2D buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053BC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 2D engine. end dHubCmd2ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053C0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053C4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053C8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053CC |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053D0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053D4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053D8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 2D buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053DC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 2D engine. end dHubCmd2ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053E0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053E4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053E8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053EC |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053F0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053F4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053F8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 2D buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000053FC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 2D engine. end dHubCmd2ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005400 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005404 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005408 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000540C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005410 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005414 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005418 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 2D buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000541C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 2D engine. end dHubCmd2ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005420 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005424 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005428 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000542C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005430 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005434 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005438 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 2D buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000543C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 2D engine. end dHubCmd2ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005440 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005444 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005448 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000544C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005450 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005454 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005458 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 2D buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000545C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 2D engine. end dHubCmd2ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005460 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005464 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005468 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000546C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005470 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005474 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005478 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 2D buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000547C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 2D engine. end dHubCmd2ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005480 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005484 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005488 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000548C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005490 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005494 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005498 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 2D buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000549C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 2D engine. end dHubCmd2ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054A0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054A4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054A8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054AC |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054B0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054B4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054B8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 2D buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054BC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 2D engine. end dHubCmd2ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054C0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054C4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054C8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054CC |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054D0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054D4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054D8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 2D buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054DC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 2D engine. end dHubCmd2ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054E0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 2D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054E4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 2ND engine |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 2ND engine |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 2D command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 2D command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054E8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054EC |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054F0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054F4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054F8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 2D buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000054FC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 2D engine. end dHubCmd2ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005500 |
Up-to 16 4ND channels. 4ND Channel[N] is connected to dHub.Channel[N] command queue, that is, dHub.HBO.Channel[2N] Note: 4ND engines are instantiated in the same way as the old 2D engine. It is allowed to have multiple 1D, 2D, 2ND and 4ND channels in a dHub. Restriction is each channel can only have one type. |
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 4D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005504 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0 |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
|
[31:30] |
0x0 |
0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005508 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000550C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005510 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005514 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 2D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005518 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000551C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 3D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005520 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005524 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 4D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005528 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000552C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 4ND engine. |
|
Access |
Register |
Address |
Description |
|
(RW) |
32'h00005530 |
|
|
|
Range |
Field |
Reset |
Description |
|
[7:0] |
0x0 |
The FLEXA stream ID |
|
|
[9:8] |
0x0 |
Consumer ID |
|
|
[10:10] |
0x0 |
When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine |
|
|
[11:11] |
0x0 |
Request for a segment without waiting for data consumer (or producer) |
|
|
[13:12] |
0x0 |
Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold; |
|
|
[14:14] |
0x0 |
Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”. |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h00005534 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[5:3] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[8:6] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
Access |
Register |
Address |
Description |
|
(P) |
32'h00005538 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00 |
|
|
[5:3] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01 |
|
|
[8:6] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000553C |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 4D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005540 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0 |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
|
[31:30] |
0x0 |
0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005544 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005548 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000554C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005550 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 2D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005554 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005558 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 3D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000555C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005560 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 4D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005564 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005568 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 4ND engine. |
|
Access |
Register |
Address |
Description |
|
(RW) |
32'h0000556C |
|
|
|
Range |
Field |
Reset |
Description |
|
[7:0] |
0x0 |
The FLEXA stream ID |
|
|
[9:8] |
0x0 |
Consumer ID |
|
|
[10:10] |
0x0 |
When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine |
|
|
[11:11] |
0x0 |
Request for a segment without waiting for data consumer (or producer) |
|
|
[13:12] |
0x0 |
Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold; |
|
|
[14:14] |
0x0 |
Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”. |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h00005570 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[5:3] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[8:6] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
Access |
Register |
Address |
Description |
|
(P) |
32'h00005574 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00 |
|
|
[5:3] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01 |
|
|
[8:6] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005578 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 4D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000557C |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0 |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
|
[31:30] |
0x0 |
0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005580 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005584 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005588 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000558C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 2D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005590 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005594 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 3D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005598 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000559C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 4D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000055A0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000055A4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 4ND engine. |
|
Access |
Register |
Address |
Description |
|
(RW) |
32'h000055A8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[7:0] |
0x0 |
The FLEXA stream ID |
|
|
[9:8] |
0x0 |
Consumer ID |
|
|
[10:10] |
0x0 |
When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine |
|
|
[11:11] |
0x0 |
Request for a segment without waiting for data consumer (or producer) |
|
|
[13:12] |
0x0 |
Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold; |
|
|
[14:14] |
0x0 |
Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”. |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h000055AC |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[5:3] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[8:6] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
Access |
Register |
Address |
Description |
|
(P) |
32'h000055B0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00 |
|
|
[5:3] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01 |
|
|
[8:6] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000055B4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 4D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000055B8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0 |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
|
[31:30] |
0x0 |
0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000055BC |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000055C0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000055C4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000055C8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 2D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000055CC |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000055D0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 3D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000055D4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000055D8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 4D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000055DC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000055E0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 4ND engine. |
|
Access |
Register |
Address |
Description |
|
(RW) |
32'h000055E4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[7:0] |
0x0 |
The FLEXA stream ID |
|
|
[9:8] |
0x0 |
Consumer ID |
|
|
[10:10] |
0x0 |
When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine |
|
|
[11:11] |
0x0 |
Request for a segment without waiting for data consumer (or producer) |
|
|
[13:12] |
0x0 |
Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold; |
|
|
[14:14] |
0x0 |
Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”. |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h000055E8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[5:3] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[8:6] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
Access |
Register |
Address |
Description |
|
(P) |
32'h000055EC |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00 |
|
|
[5:3] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01 |
|
|
[8:6] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000055F0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 4D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000055F4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0 |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
|
[31:30] |
0x0 |
0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000055F8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000055FC |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005600 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005604 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 2D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005608 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000560C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 3D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005610 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005614 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 4D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005618 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000561C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 4ND engine. |
|
Access |
Register |
Address |
Description |
|
(RW) |
32'h00005620 |
|
|
|
Range |
Field |
Reset |
Description |
|
[7:0] |
0x0 |
The FLEXA stream ID |
|
|
[9:8] |
0x0 |
Consumer ID |
|
|
[10:10] |
0x0 |
When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine |
|
|
[11:11] |
0x0 |
Request for a segment without waiting for data consumer (or producer) |
|
|
[13:12] |
0x0 |
Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold; |
|
|
[14:14] |
0x0 |
Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”. |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h00005624 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[5:3] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[8:6] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
Access |
Register |
Address |
Description |
|
(P) |
32'h00005628 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00 |
|
|
[5:3] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01 |
|
|
[8:6] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000562C |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 4D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005630 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0 |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
|
[31:30] |
0x0 |
0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005634 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005638 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000563C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005640 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 2D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005644 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005648 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 3D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000564C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005650 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 4D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005654 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005658 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 4ND engine. |
|
Access |
Register |
Address |
Description |
|
(RW) |
32'h0000565C |
|
|
|
Range |
Field |
Reset |
Description |
|
[7:0] |
0x0 |
The FLEXA stream ID |
|
|
[9:8] |
0x0 |
Consumer ID |
|
|
[10:10] |
0x0 |
When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine |
|
|
[11:11] |
0x0 |
Request for a segment without waiting for data consumer (or producer) |
|
|
[13:12] |
0x0 |
Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold; |
|
|
[14:14] |
0x0 |
Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”. |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h00005660 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[5:3] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[8:6] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
Access |
Register |
Address |
Description |
|
(P) |
32'h00005664 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00 |
|
|
[5:3] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01 |
|
|
[8:6] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005668 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 4D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000566C |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0 |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
|
[31:30] |
0x0 |
0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005670 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005674 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005678 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000567C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 2D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005680 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005684 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 3D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005688 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000568C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 4D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005690 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005694 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 4ND engine. |
|
Access |
Register |
Address |
Description |
|
(RW) |
32'h00005698 |
|
|
|
Range |
Field |
Reset |
Description |
|
[7:0] |
0x0 |
The FLEXA stream ID |
|
|
[9:8] |
0x0 |
Consumer ID |
|
|
[10:10] |
0x0 |
When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine |
|
|
[11:11] |
0x0 |
Request for a segment without waiting for data consumer (or producer) |
|
|
[13:12] |
0x0 |
Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold; |
|
|
[14:14] |
0x0 |
Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”. |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h0000569C |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[5:3] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[8:6] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
Access |
Register |
Address |
Description |
|
(P) |
32'h000056A0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00 |
|
|
[5:3] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01 |
|
|
[8:6] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000056A4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 4D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000056A8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0 |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
|
[31:30] |
0x0 |
0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000056AC |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000056B0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000056B4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000056B8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 2D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000056BC |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000056C0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 3D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000056C4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000056C8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 4D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000056CC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000056D0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 4ND engine. |
|
Access |
Register |
Address |
Description |
|
(RW) |
32'h000056D4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[7:0] |
0x0 |
The FLEXA stream ID |
|
|
[9:8] |
0x0 |
Consumer ID |
|
|
[10:10] |
0x0 |
When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine |
|
|
[11:11] |
0x0 |
Request for a segment without waiting for data consumer (or producer) |
|
|
[13:12] |
0x0 |
Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold; |
|
|
[14:14] |
0x0 |
Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”. |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h000056D8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[5:3] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[8:6] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
Access |
Register |
Address |
Description |
|
(P) |
32'h000056DC |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00 |
|
|
[5:3] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01 |
|
|
[8:6] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000056E0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 4D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000056E4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0 |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
|
[31:30] |
0x0 |
0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000056E8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000056EC |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000056F0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000056F4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 2D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000056F8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000056FC |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 3D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005700 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005704 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 4D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005708 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000570C |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 4ND engine. |
|
Access |
Register |
Address |
Description |
|
(RW) |
32'h00005710 |
|
|
|
Range |
Field |
Reset |
Description |
|
[7:0] |
0x0 |
The FLEXA stream ID |
|
|
[9:8] |
0x0 |
Consumer ID |
|
|
[10:10] |
0x0 |
When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine |
|
|
[11:11] |
0x0 |
Request for a segment without waiting for data consumer (or producer) |
|
|
[13:12] |
0x0 |
Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold; |
|
|
[14:14] |
0x0 |
Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”. |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h00005714 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[5:3] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[8:6] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
Access |
Register |
Address |
Description |
|
(P) |
32'h00005718 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00 |
|
|
[5:3] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01 |
|
|
[8:6] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000571C |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 4D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005720 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0 |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
|
[31:30] |
0x0 |
0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005724 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005728 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000572C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005730 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 2D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005734 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005738 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 3D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000573C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005740 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 4D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005744 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005748 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 4ND engine. |
|
Access |
Register |
Address |
Description |
|
(RW) |
32'h0000574C |
|
|
|
Range |
Field |
Reset |
Description |
|
[7:0] |
0x0 |
The FLEXA stream ID |
|
|
[9:8] |
0x0 |
Consumer ID |
|
|
[10:10] |
0x0 |
When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine |
|
|
[11:11] |
0x0 |
Request for a segment without waiting for data consumer (or producer) |
|
|
[13:12] |
0x0 |
Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold; |
|
|
[14:14] |
0x0 |
Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”. |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h00005750 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[5:3] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[8:6] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
Access |
Register |
Address |
Description |
|
(P) |
32'h00005754 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00 |
|
|
[5:3] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01 |
|
|
[8:6] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005758 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 4D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000575C |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0 |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
|
[31:30] |
0x0 |
0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005760 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005764 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005768 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000576C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 2D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005770 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005774 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 3D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005778 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000577C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 4D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005780 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005784 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 4ND engine. |
|
Access |
Register |
Address |
Description |
|
(RW) |
32'h00005788 |
|
|
|
Range |
Field |
Reset |
Description |
|
[7:0] |
0x0 |
The FLEXA stream ID |
|
|
[9:8] |
0x0 |
Consumer ID |
|
|
[10:10] |
0x0 |
When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine |
|
|
[11:11] |
0x0 |
Request for a segment without waiting for data consumer (or producer) |
|
|
[13:12] |
0x0 |
Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold; |
|
|
[14:14] |
0x0 |
Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”. |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h0000578C |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[5:3] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[8:6] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
Access |
Register |
Address |
Description |
|
(P) |
32'h00005790 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00 |
|
|
[5:3] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01 |
|
|
[8:6] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005794 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 4D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005798 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0 |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
|
[31:30] |
0x0 |
0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000579C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000057A0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000057A4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000057A8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 2D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000057AC |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000057B0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 3D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000057B4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000057B8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 4D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000057BC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000057C0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 4ND engine. |
|
Access |
Register |
Address |
Description |
|
(RW) |
32'h000057C4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[7:0] |
0x0 |
The FLEXA stream ID |
|
|
[9:8] |
0x0 |
Consumer ID |
|
|
[10:10] |
0x0 |
When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine |
|
|
[11:11] |
0x0 |
Request for a segment without waiting for data consumer (or producer) |
|
|
[13:12] |
0x0 |
Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold; |
|
|
[14:14] |
0x0 |
Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”. |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h000057C8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[5:3] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[8:6] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
Access |
Register |
Address |
Description |
|
(P) |
32'h000057CC |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00 |
|
|
[5:3] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01 |
|
|
[8:6] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000057D0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 4D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000057D4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0 |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
|
[31:30] |
0x0 |
0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000057D8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000057DC |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000057E0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000057E4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 2D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000057E8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000057EC |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 3D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000057F0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000057F4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 4D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000057F8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000057FC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 4ND engine. |
|
Access |
Register |
Address |
Description |
|
(RW) |
32'h00005800 |
|
|
|
Range |
Field |
Reset |
Description |
|
[7:0] |
0x0 |
The FLEXA stream ID |
|
|
[9:8] |
0x0 |
Consumer ID |
|
|
[10:10] |
0x0 |
When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine |
|
|
[11:11] |
0x0 |
Request for a segment without waiting for data consumer (or producer) |
|
|
[13:12] |
0x0 |
Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold; |
|
|
[14:14] |
0x0 |
Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”. |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h00005804 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[5:3] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[8:6] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
Access |
Register |
Address |
Description |
|
(P) |
32'h00005808 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00 |
|
|
[5:3] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01 |
|
|
[8:6] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000580C |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 4D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005810 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0 |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
|
[31:30] |
0x0 |
0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005814 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005818 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000581C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005820 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 2D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005824 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005828 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 3D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000582C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005830 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 4D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005834 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005838 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 4ND engine. |
|
Access |
Register |
Address |
Description |
|
(RW) |
32'h0000583C |
|
|
|
Range |
Field |
Reset |
Description |
|
[7:0] |
0x0 |
The FLEXA stream ID |
|
|
[9:8] |
0x0 |
Consumer ID |
|
|
[10:10] |
0x0 |
When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine |
|
|
[11:11] |
0x0 |
Request for a segment without waiting for data consumer (or producer) |
|
|
[13:12] |
0x0 |
Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold; |
|
|
[14:14] |
0x0 |
Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”. |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h00005840 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[5:3] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[8:6] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
Access |
Register |
Address |
Description |
|
(P) |
32'h00005844 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00 |
|
|
[5:3] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01 |
|
|
[8:6] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005848 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 4D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000584C |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0 |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
|
[31:30] |
0x0 |
0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005850 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005854 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005858 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000585C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 2D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005860 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005864 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 3D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005868 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000586C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 4D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005870 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005874 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 4ND engine. |
|
Access |
Register |
Address |
Description |
|
(RW) |
32'h00005878 |
|
|
|
Range |
Field |
Reset |
Description |
|
[7:0] |
0x0 |
The FLEXA stream ID |
|
|
[9:8] |
0x0 |
Consumer ID |
|
|
[10:10] |
0x0 |
When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine |
|
|
[11:11] |
0x0 |
Request for a segment without waiting for data consumer (or producer) |
|
|
[13:12] |
0x0 |
Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold; |
|
|
[14:14] |
0x0 |
Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”. |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h0000587C |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[5:3] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[8:6] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
Access |
Register |
Address |
Description |
|
(P) |
32'h00005880 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00 |
|
|
[5:3] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01 |
|
|
[8:6] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005884 |
|
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
0x0 |
DRAM data address of the 4D buffer, in bytes. |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005888 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
0x1 |
Number of bytes to transfer per step. Value of 0 is invalid and treated as 1 Equivalent to dHubCmdHDR.size |
|
|
[20:16] |
0x0 |
0: Semaphore check is disabled ID: ID of semaphore to check for the first command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, chkSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[25:21] |
0x0 |
0: Semaphore update is disabled ID: ID of semaphore to update for the last command sent out by 4ND engine Note: when semaFlexaHub.semaphoreFlexa[i].SEG_LINE is set to non zero value, updSemId won’t take effect, the corresponding channel ID will be used as Flexa semaphore ID |
|
|
[26:26] |
0x0 |
1: raise interrupt upon whole 4ND command finish. 0 : no interrupt Equivalent to setting dHubCmdHDR.interrupt on the last 4ND command. |
|
|
[27:27] |
0x0 |
Follows the definition of dHubCmdHDR.ovrdQos |
|
|
[28:28] |
0x0 |
Follows the definition of dHubCmdHdr.disSem Note: to support Flexa SBI handshaking, disSem has to be set to 0 |
|
|
[29:29] |
0x0 |
Follows the definition of dHubCmdHdr.qosSel |
|
|
[31:30] |
0x0 |
0: 4ND mode 1: 1D mode 2: 2ND mode 3: 3ND mode |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000588C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per address. Signed 24-bit 2's complement number -8M to +8M Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005890 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per dimension Value of 0 is invalid and treated as 1 Note: to support Flexa SBI handshaking, DESC_1D_SZ has to be 1, such that for every scan line defined by 1D only the 1st MTU do semaphore check and the last MTU do semaphore update |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005894 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 2D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 2D dimension specified by: DESC_1D_SZ.size * DESC_1D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h00005898 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 2D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h0000589C |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 3D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 3D dimension specified by: DESC_2D_SZ.size * DESC_2D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000058A0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 3D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000058A4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of bytes to step per 4D dimension Signed 24-bit 2's complement number -8M to +8M Value of 0 is used for a circular buffer in 4D dimension specified by: DESC_3D_SZ.size * DESC_3D_ST.step |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000058A8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[23:0] |
0x1 |
Number of steps per 4D dimension Value of 0 is invalid and treated as 1 |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000058AC |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write 1 to enable the channel. Will step through full 4ND buffer till done (!busy) |
|
Access |
Register |
Address |
Description |
|
(W-) |
32'h000058B0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[0:0] |
0x0 |
Write anything to reset the 4ND engine. |
|
Access |
Register |
Address |
Description |
|
(RW) |
32'h000058B4 |
|
|
|
Range |
Field |
Reset |
Description |
|
[7:0] |
0x0 |
The FLEXA stream ID |
|
|
[9:8] |
0x0 |
Consumer ID |
|
|
[10:10] |
0x0 |
When this bit is set, Flexa interface PR_END (for producer) or CR_END (for consumer) will be issued once the completion of frame defined by 4ND engine |
|
|
[11:11] |
0x0 |
Request for a segment without waiting for data consumer (or producer) |
|
|
[13:12] |
0x0 |
Select the FLEXA handshaking timeout thresholds at the FLEXA Synchronizer side. 0: no timeout, wait forever; 1: 1 cycle timeout; 2: short timeout threshold; 3: long timeout threshold; |
|
|
[14:14] |
0x0 |
Software can enforce Flexa data producer or data consumer to issue PR_END (stop streaming) or CR_END (to be offline) in the middle of data frame transmission through this bit, this bit will be cleared automatically by HW once PR_END or CR_END acknowledged by Flexa Synchronizer with the status of “successful”. |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h000058B8 |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b00, write ‘1’ to clear bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[5:3] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b01, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
|
[8:6] |
0x0 |
Data producer or consumer request gets abnormal status response from FLEXA Synchronizer when {p(or c)r_start, p(or c)r_end = 2’b10, write ‘1’ to clear each bit: [0]: p(or c)r_status is 2’b01, not initialized; [1]: p(or c)r_status is 2’b10, timeout error or buffer full; [2]: p(or c)r_status is 2’b11, out-of-sync |
|
Access |
Register |
Address |
Description |
|
(P) |
32'h000058BC |
|
|
|
Range |
Field |
Reset |
Description |
|
[2:0] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_00 |
|
|
[5:3] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_01 |
|
|
[8:6] |
0x0 |
Set to disable the 4ND engine FLEXA outsync interrupt generated from INTR_STA.outsync_10 end dHubCmd4ND |
|
Access |
Register |
Address |
Description |
|
(R-) |
32'h000058C0 |
|
|
|
Range |
Field |
Reset |
Description |
|
[15:0] |
|
Per channel status 0: no ongoing command is being processed 1: channel controller is busy |
|
Access |
Register |
Address |
Description |
|
(RW) |
32'h00005900 |
end dHubReg2D Internal memory |
|
|
Range |
Field |
Reset |
Description |
|
[31:0] |
Memory |
|
Memory |